FIG. 1 is a schematic view of a processor system architecture. The system has a central processor unit (CPU), which receives a clock. The CPU is connected to a memory block 50. Although there are various possible memory configurations, the block shown in FIG. 1 contains a random access memory (RAM), an error detection unit and an error correction unit. The processor system also includes other devices. For example, the device may have a peripheral, as shown in FIG. 1. The clock signal is supplied not only to the CPU, but also to the memory block 50 and the peripheral.
The clock system shown in FIG. 1, in which the system clock is distributed to all blocks, is typical. Sometimes, there is a task which cannot be completed in a single clock cycle clock. In this case, one of the blocks shown in FIG. 1 is slower than the other blocks. One example of such a task is correction of a soft error in a memory. A soft error in memory is an error caused when data in the memory gets corrupted. In this case, the data was correct when it was written in the memory. Subsequently, however, one or more bits of the memory became inverted, perhaps due to alpha radiation. A soft error in memory is detected, for example by the parity detection, only when the CPU reads from a location within the RAM of the memory block, and that location contains a soft error. To correct the error and make the corrected data available for the CPU requires one or more additional clock cycles.
Soft errors in memory are fairly rare. However, when they occur, they must be corrected, and an extra clock cycle is required to do this. The processor expects the memory to return the information in a single clock cycle. If the memory simply delays, problems will result in the processor pipeline, which is connected to memory interfaces.
One way to handle correction of soft errors in memory is to add wait states to the system. Wait states require additional logic and flip-flops to handle a hand shaking mechanism. The additional logic increases the size of the chip and affects speed. Adding wait states could also require changes to the architecture of the CPU or other blocks of the system.